Cyclone V Nios/FPGA Configuration

Oh I'm sorry I thought I put the kit on there, its the Cyclone V E Development Kit: DK-DEV-5CEA7N. There is no ARM processor, its a pure FPGA board, so the TSE is connected to the FPGA fabric. Really my question is how to go about setting up the NIOS to run off the DDR3, as well as having the FPGA be able to have addressable access, and having the TSE have access as well. I was thinking about setting up the DDR3 into three separate sections, two data buffers that could be accessed by the FPGA, NIOS, or TSE. And the last section being the area for the NIOS itself. But I have no idea how to do it.