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alberto_p's avatar
alberto_p
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6 years ago

Cyclone V Jtag programming Failed

Dear all, I am a newbie here, so excuse me if I am in the wrong place to ask. I have the following problem: I have a custom made board with a Cyclone V FPGA (5CGX). I have 3 usb blasters Terasic (...
SreekumarR_G_Intel's avatar
SreekumarR_G_Intel
Icon for Frequent Contributor rankFrequent Contributor
6 years ago

Hello there,

Interesting one ..quick thought ....Can you check with 6 MHz frequency? I believe by default it is 24 MHz.

Thank you,

Regards,

Sree

alberto_p's avatar
alberto_p
Icon for New Contributor rankNew Contributor
6 years ago

Hello,

thanks for the answer.

The frequency is 6 MHz... I searched around to change it but it seems to be the minimum frequency you can set.

In the meanwhile I tried again with the Jtag Chain Debugger and the IDCODE iteration test. It looks like, when I go up with iterations there is something wrong. I have a "Warning: Uncertain JTAG chain. Detected 1 device(s)". Not fully clear what it means but I am starting to think that, on a single iteration or with a few iterations, it works. As soon as I go high with iterations (which is also the case of a .sof file programming), there is something wrong with the bus. It is something that statistically happens: I cannot see it with a low number of iterations but when I go high it appears... Now, what exactly it is (TCLK, TDI, TDO...all of them..why it works with one bluster and not with the others....something else..)...no idea.

Regards.