Forum Discussion
Altera_Forum
Honored Contributor
9 years agoI think that if the external clocks comes from one of the pins in the HSMC itself, it would be possible to perform a loopback in the FPGA (at the cost of additional jitter) to the HSMC clock in. Not sure about the supported banks though. My idea is something like this:
http://www.terasic.com.tw/cgi-bin/page/archive.pl?language=english&categoryno=67&no=129&partno=1