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ANBARASU's avatar
ANBARASU
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1 year ago

CYCLONE V FPGA POWER-UP SEQUENCE

Currently i am using the below cyclone V FPGA for my design, Part: 5CGTFD7D5F27I7N As per the CV-52001 (2023.10.18) -Volume 1: Device Interfaces and Integration The recommended power-up sequence g...
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ANBARASU's avatar
ANBARASU
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1 year ago

Hi Farbi,

As above mentioned, there is no sequence order required in group 2, But i could see the below statement.

Here i am using Bank 3B/4A and Bank 7A/8A uses VCCIO as 1.35V and VCCPD as +2.5V.

These 2 bank voltages alone i am using VCCIO and VCCPD as different voltages, other bank voltages either 3.3V or +2.5V for both VCCIO and VCCPD are same.

Query:

If i understood correctly if i enable 3.3V first in the group 2 and followed by +2.5V/1.35V together i will meet the NOTE 35 point. Please confirm.

Farabi's avatar
Farabi
Icon for Regular Contributor rankRegular Contributor
1 year ago

Hello,

Please make sure you follow this pin connection guideline, link : https://cdrdv2-public.intel.com/654351/pcg-01014.pdf

1. If you have same VCCIO voltage with VCCPD, you may connect the power rail to the same voltage regulator and power up together.

2. If you have VCCIO less than 2.5V, for eg. you connect VCCIO to 1.35V, VCCPD located in the same IO bank must be supplied by 2.5V. For this case, you need to power VCCPD 2.5V first, followed by VCCIO 1.35V to avoid current transient.

Back to your question: "If i understood correctly if i enable 3.3V first in the group 2 and followed by +2.5V/1.35V together i will meet the NOTE 35 point. "

<ANS> Yes, correct.

regards,

Farabi