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ANBARASU's avatar
ANBARASU
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1 year ago

CYCLONE V FPGA POWER-UP SEQUENCE

Currently i am using the below cyclone V FPGA for my design, Part: 5CGTFD7D5F27I7N As per the CV-52001 (2023.10.18) -Volume 1: Device Interfaces and Integration The recommended power-up sequence g...
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Farabi_Altera's avatar
Farabi_Altera
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1 year ago

This is power sequence timing diagram:

this is tRAMP you need to follow:

regards,
Farabi

ANBARASU's avatar
ANBARASU
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1 year ago

Hi Farabi,

Thanks for your response!

Regarding the below query, to avoid VCCPD current transient i should follow above "power sequence timing diagram (Figure 183)". Please confirm.

As per the table 10-1 , point 33 is not clear for me, can anyone help to provide more details.

Regards,

Anbarasu S