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ANBARASU's avatar
ANBARASU
Icon for New Contributor rankNew Contributor
1 year ago

CYCLONE V FPGA POWER-UP SEQUENCE

Currently i am using the below cyclone V FPGA for my design, Part: 5CGTFD7D5F27I7N As per the CV-52001 (2023.10.18) -Volume 1: Device Interfaces and Integration The recommended power-up sequence g...
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Farabi_Altera's avatar
Farabi_Altera
Icon for Regular Contributor rankRegular Contributor
1 year ago

Hello,

Another thing you need to make sure, please make sure the power ramp up for all power rails are ramping up monotonously(meaning no plateau during the ramping up). If there is plateau during ramp up, the POR circuit will trigger the device into reset mode again and not complete the power up activity.

regards,

Farabi