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ramsoffer_123's avatar
ramsoffer_123
Icon for Occasional Contributor rankOccasional Contributor
3 years ago
Solved

cyclone v ddr3

hey to you all, im trying to interface to ddr3 component with the ddr3 uniphy controller ip . im using cyclone v soc development kit with quartus version 14.1 . i succeded to run the example d...
  • ramsoffer_123's avatar
    ramsoffer_123
    3 years ago

    hello again,

    ok i think i understands the addressing now.

    the address[29:0] uses only [29:4].(26 bits out of 30). and the 4 bits left are just padding.

    correct me if im wrong.

    thanks,

    Ram.

AdzimZM_Altera's avatar
AdzimZM_Altera
Icon for Regular Contributor rankRegular Contributor
3 years ago

Hi Ram,


Thank you for submitting your question in Intel Community.

I'm Adzim will assist you in this thread.


The avalon local address is a parameter that store the location of the bank that to be accessed during the read and write memory transaction.

It's combination of chip select bits + row bits + bank bits + column - N where N is 1 for full-rate controller and 2 for half-rate controller.

The order of address mapping is based on the "Local-to-Memory Address Mapping" setting in the IP.


The memory address is determined the operation of the memory. This can be referred to memory datasheet in the truth table.


For read and write operation, there is timing diagram that illustrated the read and write operation in the EMIF handbook volume 3 starting on page 440.

Link: https://www.intel.com/programmable/technical-pdfs/683841.pdf#page=440


Regards,

Adzim