Cyclone V 5CEFA2F23C8N stuck in configuration error loop.

Hi,

I have a Cyclone V FPGA with Intel EPCQ32A configuration device attached, and I appear to be stuck in a configuration error loop. I observe that CONF_DONE is never asserted, but nSTATUS toggles up and down, with low (asserted time) around 200us, and high around 600us repeatedly.

I am in JTAG mode, and there is no other access to the EPCQ32. I only have the .jic file from the manufacturer that I'm working with, and it was generated with Quartus version 13.0.1 build 232. I have the Prime Programmer Lite edition version 18.1.0 build 625. MSEL[4:0] pins are 10011/Active Serial Standard, but I understand that this doesn't matter in JTAG mode. I have checked all pullups and power supplies for correctness. I have checked the quality of my connections, such as DCLK, as well for any possible signal integrity issues.

When I program the EPCQ, the SFL is loaded, the EPCQ is programmed, and the verify operation succeeds (CRC passes). When I do a readback, using 'Examine,' the readback file differs by the header (which contains tool version information), and the same four bytes near the end, past the 32Mbit/4194304Byte boundary. Since this looks like some sort of encapsulation around the actual EPCQ image, I tend to think that this is not a problem. Is it?

Upon power cycle, CONF_DONE never asserts, nCONFIG stays high, and nSTATUS toggles, as described above.

I don't understand what error is encountered by the FPGA when configuration data is loaded to it. How do I debug this? Is there something else I could be doing wrong?

Thanks.