Cyclone V 5CEFA2F23C8N stuck in configuration error loop.

Hi Wolfgang,

Thank you for your reply.

What I see from ADV1831 is that the data hold time requirement has gotten smaller, which is normally a good thing. But that document references another document, which I will need to dig into.

New development:

What I have observed in probing the configuration phase further is that I am getting an error because CRC does not pass. CRC does not pass because the FPGA ignores the first four bits of read data during a Fast Read command. Therefore all read data is shifted by a nibble, which is obviously wrong. THe FPGA performs the CRC check and fairly immediately restarts.

My guess is that the original jic file, which was targeting the Micron N25Q032A13ESE40G NOR flash, has a different dummy cycle setting from the new EPCQ32A part. In the EPCQ32A spec, I don't see a way of changing the number of dummy read cycles.

I don't have the luxury of the .sof file, so I seem out of luck with generating a new jic that targets the EPCQ32A. Any possible workarounds for that?

Thanks.