Forum Discussion
Altera_Forum
Honored Contributor
11 years agoI may try to answer this myself, since a MSI is a write to a given address with some payload, I can't se anything special required to generate the MSI except to create a CRA translation entry to translate the NIOS II write to the RC interrupt controller instead of to the RC DDR address.
The component mentioned may be a dedicated Master with the req / ack hooks required for some other hardware block to launch the interrupt.