Forum Discussion
Altera_Forum
Honored Contributor
14 years ago --- Quote Start --- Here are the signal names: cal_clk, clk_0, pcie_rstn_pcie_compiler_0, refclk_pcie_compiler_0, rx_in0_pcie_compiler_0, and tx_out0_pcie_compiler. --- Quote End --- I'd be pretty concerned about not connecting signals called clock. I would recommend creating a Modelsim simulation for your design. Altera has been sending out emails regarding a PCIe webinar lately. I have not watched it, but it might have something interesting in it http://www.altera.com/education/webcasts/all/source-files/wc-2011-pcie-technology-design-fpga/player.html Cheers, Dave