Cyclone IV GX starter kit SSRAM access

It looks like the JTAG to Avalon Master Bridge used in bts_general sample code doesn't support burst transfers. Since the bridge has a 32bits bus and the SRAM has 16bits so there is a burst of 2 transfers seen on the SRAM data bus. I would expect the 2 data transfers on the SRAM bus take 2 clocks but it takes a lot more as seen on SignalTap(of course, if you consider the command on the SRAM bus it would take more than 2 clocks but 2 clocks are enough for the data only). Maybe there is a way to optimize the timing of the transfer by choosing the parameters.