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Altera_Forum's avatar
Altera_Forum
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13 years ago

Cyclone IV GX starter kit SSRAM access

Hi, if anyone made the link work, could you share a link or some tips? I checked the schematic. It seems the control signals to the ISSI SSRAM need to go through the MAX II chip(EPM2210) since the Cy...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

I set the first data to 0x12345678 and saw it on SignalTap on the FSML bus for both read and write, cool. But it takes about 40 clocks at 50MHz to get that 4 bytes of data out. Maybe I didn't set some parameters properly in Qsys for the CFI related components. I would expect a date rate comparable to a DDR device(maybe a bit slower since it has only a 16bit data bus).