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Altera_Forum
Honored Contributor
11 years agoI guess some device in your sopc uses some memory (1kB, according to DLR usage difference) which 10.1 implemented with block RAM, while 12.1 now synthesizes with logic cell registers. Probably Qsys and SOPC builder optimiize the design in different ways.
Check device options in Qsys: for some of them you can explicitly select to use registers rather than block RAM. You can also browse Quartus Fitter report in order to show resource utilization for each design entity.