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Hi everyone,
i have a problem with a small example configuration of a Nios II System using DDR.
I use quartus 8.1 full license.
I get fitting errors which tell me the following:
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Error: Can't place pin ddr_mem_dqs[1] to location T8
Error: Can't place VREF pin T6 (VREFGROUP_B3_N0) for pin ddr_mem_dqs[1] of type bi-directional with SSTL-2 Class II I/O standard at location T8.
Error: Too many output and bidirectional pins per VCCIO and ground pair in I/O bank 3 when the VREF pin T6 (VREFGROUP_B3_N0) is used on device EP3C25F324C6 -- no more than 9 output/bidirectional pins within 12 consecutive pads is allowed when voltage reference pins are driving in, but there are potentially 10 pins driving out.
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I was told by someone else, that this error occurs because of a pin that has been assigned twice. But i don't find any information about that!
Does anyone know how to solve this problem?
Best regards,
Frank
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Frank,
This can also occur when there are conflicting I/O Standards selected.
In this case you have too many Output/BiDirectional pins on IOBANK 3.
Mike
Honored Contributor
