Honored ContributorI am curious as to how the control panel actually works. It seems to require the FPGA be reconfigured to work. How does the host machine exchange data with the FPGA to do things like turn on/off LEDs, read/write memory.
The only connection between the PC and the FPGA is a JTAG-over-USB link, which cant do data transfer(or so i thought). How is the data actually exchanged?
Honored ContributorI also want to know.
Honored ContributorThe control panel utilizes virtual jtag interface. The PC application controls USB Blaster through a DLL.
Honored ContributorThank FvM for your replay.
I have more questions. what is DLL? I didnt see any port of virtual jtag in schematic of HW.How it working? If i want to use virtual jtag,what documents should i read?Honored ContributorA DLL is a piece of PC software. There are actually two alternative methods used by different controlpanel versions, either using an alt_jtaglib.dll or FTD2XX.DLL directly. Both are undocumented, however.
There have been some discussions related to virtual JTAG recently in the forum, also regarding partly missing documentation. For the FPGA respectively Quartus side, it's practicable documented, particularly in sld_virtual_jtag Megafunction User Guide. The Megafunction is availabe from Megawizard for user specific applications, but also used internally for all JTAG based soft tools, e. g. PFL, SFL, Source&Probe or In-System Memory Content Editor, SignalTap. From the PC side, Quartus offers a Tcl shell for virtual JTAG commands only, also some tools to operate a virtual UART with NIOS II. Knowing the virtual JTAG coding, you could also connect it with third party JTAG interfaces or by directly accessing USB Blaster (as the said Control Panel does).Honored ContributorI don't know about this particular case, but not all control panel versions use the virtual jtag interface. The DE2-70 control panel is Nios based using virtual jtag. But I think DE1 and the plain (old) DE2 control panels handle the JTAG pin signals directly.
If the tcl scripting interface is enough for you, then virtual jtag is a better alternative.Honored ContributorIn my view, any data exchange through JTAG other than direct device configuration is a kind virtual JTAG activity. It may use different access points at PC side, but has no other option than routing data through virtual JTAG hub, using the respective protocol.
Honored ContributorHonored ContributorYes you're right, they use the LINK_Dx pins. Thank you for the clarification.
Honored ContributorTo All Guru(s) and altera experts, please help. I am using Cyclone III starter Board. I have a simple design that requires run-time reconfiguration. I do not want to use Nios or USB cores. My questions are regarding the final design when I move my prototype to be an actual hardware, would I be still able to use JTAG through the USB connector? can I use Altera schematic to include the USB connector? Is what I am saying doesn't make sens? Can I use the JTAG 10 pins (Boundary Scan) in my final design and connect them to act as serial UART so I can use my PC to reconfigure the design?
Is using the sld_virtual_jtag Megafunction would be valid in the final design or it is only on the starter board? This is my first design ever on a FPGA, I don't even know how to move my design to an actual hardware. So please bare my ignorant and questions. Thanks in advance.Honored Contributorhello,
i am trainee and i have a problem when i install the bemicro Cyclone III development board. In fact, i need to install that:“<install directory>\programmer\setup.exe”.When i do that , i obtain that kind of error : cannot copy FtDI interface DLL to target folder Someone could help me please ?:)
