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Altera_Forum
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15 years ago

Cyclone III LVDS clocking

I am interfacing an ADC (AD9461) to the HSMA breakout board on my Cyclone III dev board. The ADC is 16-bits clocked at 7MHz. I measured this LVDS signal at 1.5V high and 1.0V low, which I assume co...
Altera_Forum's avatar
Altera_Forum
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15 years ago

Thanks for the encouragement. It looks like the ALTLVDS block allows you to only assign the positive differential pin and then it assumes the negative pair pin in the design. This locks you in to using only differential pins to drive the block, which is probably a good idea anyhow. On the CIII Kit HSMC header there appears to be designated Tx and Rx differential pins. Since I'm only driving data into the board, and I'm running out of Rx pins, I tried using the Tx pins as input pins. Seems to work okay in my initial tests. Any reason I can't use the Tx pins as input pins?