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The problem is, that part of the MAX II logic, particularly the USB Blaster function, must be expected protected Altera IP that unfortunately won't be disclosed. This is a serious obstacle when intending a user defined MAX II logic including the USB Blaster functionality. At best, Altera would find a way to pack the USB Blaster to an encrypted core, that is bound to the Dev Kit.
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Is the protocol to program Altera ICs (via JTAG) protected?
I would imagine that the IP in Altera's Cyclone II Kit (MAX 3000 CPLD - EPM3128AT) or the standalone USB Blaster (EPM7064), could be re-written based on the (published?) protocol, no?
For example, something like
opencores.org has a JTAG IP, which should implement the same jtag programming that the Blaster does... am I missing something?
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