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Altera_Forum's avatar
Altera_Forum
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17 years ago

Cyclone III development board and USB FT245BL

Hi, I currently develop with the cyclone III development board (EP3C120N). The board features two USB chips. The Cypress chip is used for the byteblaster logic and as I understand the documenta...
Altera_Forum's avatar
Altera_Forum
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17 years ago

He is using an FTDI USB-232 converter. I think the latency timer is not specific to FIFO mode. If I'm correct, he is already limited by exactly the same latency.

The latency timer affects only small transfers, less than 64 bytes. As soon as the 64 bytes buffer is filled, then the timer is not relelvant.

You still get a significant latency no matter what. USB is not a low latency protocol.