Hi jaguilar,
1- What is this board? Is it a board designed by yourself, or a evaluation kit from Altera? https://www.intel.com/content/www/us/en/products/details/fpga/development-kits/cyclone/10-lp-evaluation-kit.html
If it is our development kit board, it is easier for us to understand the schematic.
If it is not our development kit, what is the FPGA configuration scheme on board? For example, is it AS, PS or FPP?
https://www.intel.com/content/www/us/en/docs/programmable/683777/current/configuration-and-remote-system-upgrades-25917.html
2- As you mentioned that "I was able to check some of the pins with VCC to be sure that the FPGA is being powered correctly and it seems ok", does it mean the power supply and function of the original FPGA logic was working normally? To better understand the status of the FPGA, you may also check the waveform of nSTATUS, CONF_DONE signals of the FPGA after power on the board to understand if it could be configured normally.
3- In Quartus/Programmer window, could you open the "Tools --> JTAG chain debugger ", then click on "Test JTAG chain" to see what is showing in the session log?

Best Regards,
Xiaoyan