Forum Discussion
milenko121175
New Contributor
New ContributorCyclone 10GX Reference Design - Cyclone10GX_PCIeGen2x4_DMA_18_0 fails during enumeration.
Hello, This post would seem to be near identical to: https://community.intel.com/t5/Programmable-Devices/Intel-pcie-gen-2x4-example-design-with-avlonmm-dma-reference/m-p/1472443 But I have verifie...
hareesh
Frequent Contributor
Frequent ContributorHi,
You are using the new version of Quartus. the problem is that the example design can support the Quartus 18.0 version. In the newer version, you can see some more new features to that IP like new signals, data width, etc.. if you update the older designs ip's in a new version the signals of the new version ip's will be in an open state only. because of that, it shows errors. if you need to compile this please use Quarts 18.0 version only.
in the above image, you can see successfully compiled in Quartus 18.0.
