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milenko121175's avatar
milenko121175
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3 years ago

Cyclone 10GX Reference Design - Cyclone10GX_PCIeGen2x4_DMA_18_0 fails during enumeration.

Hello, This post would seem to be near identical to: https://community.intel.com/t5/Programmable-Devices/Intel-pcie-gen-2x4-example-design-with-avlonmm-dma-reference/m-p/1472443 But I have verifie...
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hareesh's avatar
hareesh
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3 years ago

Hi,


I am checking this issue. if you don't mind could you please check the pin assignment I am thinking problem with the pin assignment. please cross-check whether have you assigned it correctly or not.


Thank you,



  • milenko121175's avatar
    milenko121175
    Icon for New Contributor rankNew Contributor
    3 years ago

    Hello Hareesh,

    Thank you for looking into my problem. I am not sure what you mean by my assigning pins correctly. This is the reference design that has been downloaded directly from Intel from here:

    https://www.intel.com/content/www/us/en/design-example/714945/cyclone-10-gx-pcie-gen2-x4-dma.html

    The only changes I have made is that Quartus forces me to upgrade the IP. A quick view between the Avalon reference design and this one and I can agree that the assignments look different. But I don't know what is right as I am new to Altera/Intel. This was supposed to help me learn and in my humble opinion - this should have worked "as downloaded". It is listed as current on the Intel website. If the pin assignment is wrong, can you correct please and update the Intel content where this is downloaded from? Or at least correct and send me the right version.

    Thanks in advance,

    Mil