Occasional Contributor
Frequent ContributorHi
Can you share with us a sample design that is causing the issue?
Thanks.
Eng Wei
Occasional Contributor您好，不好意思，现在才看到您的回复，下面这个是我用20.1_pro的软件建立的工程，非常期待您的解答。
Frequent ContributorI am sorry for overlook your response here. Let me take a look and get back to you.
Eng Wei
Frequent ContributorHi there
We looked at the design and the issue seems to be from the generated SDC file of the LVDS SERDES IP. We created a standalone LVDS SERDES design with the same setting as your design does, and we don't see such error exist.
Few things we want to point out:
1. there are unconstraint clocks in the design, though those unconstraint clocks don't seem related to this issue after we fixed them.
2. we switched the LVDS SERDES IP from soft-CDR to RX DPA mode, and we see that this error goes away.
3. We created a simple design with just the LVDS SERDES IP with all the similar setting, and we don't see this error happened. We compare the generated SDC file with the one in your design, and both SDC files are the same.
Questions:
1. Do you upgrade the IP which is generated from other Quartus version? From the Quartus setting file, we saw that the original Quartus version was 17.1.
thanks
Eng Wei
Frequent ContributorHi there
I hope you have your issue resolved. Since we do not receive any response from you to the previous reply that have been provided, this thread will be transitioned to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.
Eng Wei
