ContributorHello,
I have the kit and downloaded all the reference.
But I am not able to see the design of SYS MAX10-CTRL.
The max project within is for PFL configuration.
Am I missing something or please show me where it it?
Thank you!
BRs,
Johnson
Regular ContributorHi Johnson Lee,
Thanks for the clarification. The MAX 10 file available in the zip file is indeed system MAX 10 design. It is norm to find PFL IP in the system MAX 10 design. The reason is because in Fast Passive Parallal Configuration, MAX 10 is the host and it is getting the configuration file from memory and program the FPGA.
Meanwhile the configuration MAX 10, is actually the on-board USB Blaster, which it is used to program the memory device (in JTAG mode) with FPGA programming file.
Regards,
YL
Occasional ContributorI have read the code in MAX10 which is actually the code for U3 MAX(CFG) you can provide me a flash file *pof for U2 MAX10 (SYS) in kit DK-DEV-10CX220-A
Regular ContributorHi Johnson Lee,
MAX 10 design is available in the kit collateral available at link below:
https://www.intel.com/content/www/us/en/programmable/products/boards_and_kits/dev-kits/altera/cyclone-10-gx-development-kit.html
Once you have downloaded the zip file, you may find the design in directory below:
...\Cyclone 10 GX\examples\system_max10
Thank You
Regards,
YL
ContributorHi YL,
Thank you for reply.
I did this and found the content inside the folder "system_max10" is CFG MAX not SYS MAX.
Can you confirm this ?
Thank you!
Regards,
Johnson
Regular ContributorHi Johnson Lee,
There is only 1 MAX 10 in the development kit. This is the file for system max 10.
Regards,
YL
ContributorHi YL,
I attached the schematic for this kit for your reference.
Thank you!
BRs,
Johnson
