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JLee25's avatar
JLee25
Icon for Contributor rankContributor
6 years ago

Cyclone 10 GX Source Project for SYS MAX10-CTRL

Hello, I have the kit and downloaded all the reference. But I am not able to see the design of SYS MAX10-CTRL. The max project within is for PFL configuration. Am I missing something or please ...
YuanLi_S_Intel's avatar
YuanLi_S_Intel
Icon for Regular Contributor rankRegular Contributor
6 years ago

Hi Johnson Lee,

Thanks for the clarification. The MAX 10 file available in the zip file is indeed system MAX 10 design. It is norm to find PFL IP in the system MAX 10 design. The reason is because in Fast Passive Parallal Configuration, MAX 10 is the host and it is getting the configuration file from memory and program the FPGA.

Meanwhile the configuration MAX 10, is actually the on-board USB Blaster, which it is used to program the memory device (in JTAG mode) with FPGA programming file.

Regards,

YL

TRAN_HIEU_007's avatar
TRAN_HIEU_007
Icon for Occasional Contributor rankOccasional Contributor
5 years ago

I have read the code in MAX10 which is actually the code for U3 MAX(CFG) you can provide me a flash file *pof for U2 MAX10 (SYS) in kit DK-DEV-10CX220-A