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OlegT's avatar
OlegT
Icon for Occasional Contributor rankOccasional Contributor
4 years ago
Solved

Cyclone 10 GX FPGA Development Kit - PCIe AvalonMM-DMA example

Hello. I use AN829 as starting point of my design. In Platform Builder I see, that PCIe hip is connected to DDR3 emif via avalon MM bus. Both components use different clock sources, but they ar...
  • KhaiChein_Y_Intel's avatar
    KhaiChein_Y_Intel
    4 years ago

    Hi Oleg,

    Thanks for your patience while I was checking the design.

    If you refer to the Platform Designer: Interconnect Requirements, there are some settings that allow the software to automatically insert the clock crossing adapters and add pipeline stages to the Platform Designer interconnect when you generate a system.

    In our case, the clock crossing adapter type is set to FIFO and maximum pipeline stages is set to 4.

    Thanks

    Best regards,

    KhaiY

KhaiChein_Y_Intel's avatar
KhaiChein_Y_Intel
Icon for Regular Contributor rankRegular Contributor
4 years ago

Hi Oleg,


The Clock Crossing Bridge allows pipelined read masters to post multiple reads to the bridge even if the slaves downstream from the bridge do not support pipelined transfers. Before using the clock crossing bridges in your design, you should

carefully consider their effects. The bridges can have any combination of the following effects on your design:

  • Increased Latency - it has an effect on the read latency between the master and the slave.
  • Limited Concurrency - Placing a bridge between multiple Avalon-MM master and slave ports limits the number of concurrent transfers your system can initiate.
  • Address Space Translation - The slave port of a pipeline or clock crossing bridge has a base address and address span.


Thanks

Best regards,

KhaiY