Cyclone 10 GX Development Kit malfunction

Hi,

I've been working with the Cyclone 10 GX Development Kit without problems for weeks developing an IP stack solution using Ethernet. Recently the board's behaviour changed so that the link is never detected anyomore. I tried to go back to the original board examples (cyclone-10-gx-kit-collateral package), but it doesn't work with those either.

Current behaviour is like this:

1. When starting BTS the standard configurations (DDR, FMC, Simple Socket Server) can be loaded but they seem not to work properly: the DDR test project reports DDR Calibration Error, and using the Simple Socket Server no IP address is assigned to the board. (See screenshots.)
2. After loading the Simple Socket Server's .sof file via BTS, I am able to download my .elf file from the NIOS II Sw Build Tools for Eclipse , but the behaviour is the same: the Ethernet link is never established.
3. Downloading .sof files into the 10CX220Y FPGA is possible via the Quartus Prime Programmer, too, after which, again, I am able to load by .elf from the NIOS II Sw Build Tools for Eclipse, but funtionality is the same as described above.
4. The MAX 10 can be programmed via BTS or Progammer.
5. Factory Restore from BTS is not working. In the Erase phase the status indicator does not move, Erase phase finishes in cca. 3 seconds, then during Writing the status indicator doesn't move either, and after a few seconds a window is popped up, saying "Write timeout". (See screenshot.)
6. At a JTAG speed of 24MHz, the CFI NOR flash connected to the MAX 10 can be erased, but when trying to load a .pof file (that I generated myself based on a .sof) into it, it fails wither when programming the first page or after successfully programming a few pages.
7. When lowering the JTAG speed to e.g. 6MHz (possible with v19.2 of the Quartus Prime Pro package), the CFI NOR flash can be programmed successfully.
8. When power cycling the board after the successful CFI NOR flash programming (6.), the red Configuration Failed LED enlightens. Downloading an .elf file from the NIOS II Sw Build Tools for Eclipse is not possible as no bebug connection is found in NIOS II Sw Build Tools for Eclipse's Debug Configurations.
9. Erasing the EPCQL1024 device is not possible. In the Programmer I select a .jic file for the 10CX220Y FPGA, so the EPCQL1024 device appears as one connected to the 10CX220Y. Then I check Program/Configure for the 10CX220Y and Erase for the EPCQL1024. Using a lower JTAG frequency the status indicator goes to 22% (using 24MHz it remains on 0%), then it fails. Using version 17.1 the message is "Operation failed". Using version 19.2 the message is "Error(209025): Can't recognize silicon ID for device 3. A device's silicon ID is different from its JTAG ID. Verify that all cables are securely connected, select a different device, or check the power on the target system. Make sure the device pins are connected and configured correctly. " (See screenshot.)
10. Downloading a .jic file into the EPCQL1024 is not possible. Same as previous point.

The Quartus Prime software versions used are:

17.1

19.2

Behaviour is quite the same using both.

Thanks in advance for your help.