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manishkumar's avatar
manishkumar
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2 years ago

Cyclone® V FPGA – Remote System Upgrade over UART Based on Nios® II Processors with EPCQ Design Exam

with given reference design example try to program the output_file.jic file through Quartus prime programmer as per the reference user manual in to the (Cyclone V E FPGA Development Kit) , but it is...
Fpga Devkit
NurAiman_M_Intel's avatar
NurAiman_M_Intel
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2 years ago

Hi,


Can you provide the snapshot of the top marking of the FPGA in order for us to confirm the part number?


Just for confirmation, you are using Remote System Upgrade over UART Based on Nios® II Processors with EPCQ Design Example, and generate the .jic file from it. Is that correct? How do you generate the .jic file?


Regards,

Aiman