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manishkumar's avatar
manishkumar
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2 years ago

Cyclone® V FPGA – Remote System Upgrade over UART Based on Nios® II Processors with EPCQ Design Exam

with given reference design example try to program the output_file.jic file through Quartus prime programmer as per the reference user manual in to the (Cyclone V E FPGA Development Kit) , but it is...
Fpga Devkit
NurAiman_M_Intel's avatar
NurAiman_M_Intel
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2 years ago

Hi,


I am testing this from my end. Will provide you an update soon.


Regards,

Aiman


  • manishkumar's avatar
    manishkumar
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    2 years ago

    Hi,

    any update to resolve the silicon id mismatch error.

    Regards,

    Manish