Forum Discussion

New Contributor

1 year ago

Cyclone® V FPGA – Remote System Upgrade over UART Based on Nios® II Processors with EPCQ Design Exam

with given reference design example try to program the output_file.jic file through Quartus prime programmer as per the reference user manual in to the (Cyclone V E FPGA Development Kit) , but it is...

Fpga Devkit

NurAiman_M_Intel

Super Contributor

1 year ago

Hi,

In Cyclone V E board reference manual, the block diagram shows that it has EPCQ and 512 flash. If you are using EPCQ, you will need to create .jic file by choosing active serial and ECPQ256 not EPCQ512. Then you may program the .jic file through Quartus programmer. Can you please try this and see if it works?

https://www.intel.com/content/www/us/en/content-details/654026/cyclone-v-e-fpga-development-board-reference-manual.html

Regards,

Aiman

Forum Discussion

Cyclone® V FPGA – Remote System Upgrade over UART Based on Nios® II Processors with EPCQ Design Exam

Recent Discussions

Regarding Quartus Prime License Activation for the Agilex 5 Evaluation Kit

Stratix 10 FPGA Dev Kit VCCIO_FMC voltage issue

DE10-Lite unable to flash?

Mandelbrot viewer on Cyclone V - Platform Designer layout

A question about reading the configuration space of the R-Tile PCIe IP EP