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manishkumar's avatar
manishkumar
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1 year ago

Cyclone® V FPGA – Remote System Upgrade over UART Based on Nios® II Processors with EPCQ Design Exam

with given reference design example try to program the output_file.jic file through Quartus prime programmer as per the reference user manual in to the (Cyclone V E FPGA Development Kit) , but it is...
Fpga Devkit
NurAiman_M_Intel's avatar
NurAiman_M_Intel
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1 year ago

Hi,


  1. For confirmation, you are using Cyclone V E dev kit?
  2. What is the Quartus version that was used?
  3. You are using EPCQ flash?
  4. You are using USB Blaster 1 or II?.
  5. Make sure your MSEL setting is correct.
  6. Check the FPGA and flash connection.
  7. Try to check the connection of Intel FPGA Download Cable to header available on the board.

Refer the below link,

https://www.intel.com/content/www/us/en/programmable/support/support-resources/knowledge-base/solutions/rd12132011_913.html


Regards,

Aiman


manishkumar's avatar
manishkumar
Icon for New Contributor rankNew Contributor
1 year ago

Hi,

Answer to your queries:

1) using Cyclone V E dev kit

2) Quartus Prime lite edition 18.1

3) using EPCQ Flash (EPCQ256 mentioned in CycloneV E dev kit schematic and BOM)

4) using USB Blaster II connected to J10 connector of CycloneV dev kit

5) MSEL setting is MSEL{4:0} 10010 AS mode
6) using CycloneV E dev kit, so bydefault connection is present

7) properly connected and FPGA is detected on Quartus prime programmer (screenshot attached)