Occasional Contributor
Frequent ContributorHi Sir,
After the design generation, do you change the directory? I am asking this because usually the QSYS_SIMDIR should work one.
I run the same simulation using QII18.0 and I can run the simulation successfully.
Maybe you can try to hard code the QSYS_SIMDIR for this line as well.
set memory_files [concat $memory_files [pcie_example_design_tb::get_memory_files "$QSYS_SIMDIR"]]
If it still fails, then skip the copy in the tcl, and manually paste the hex file in the mentor directory.
I attach the hex file here.
Occasional ContributorHi BoonT,
Thanks for your reply.
No, i did not change the directory. I tried more variants, like using $QSYS_SIMDIR in the directory string, but whatever level ../i used, it couldn't find the files. I had to use the direct path in line 1, 2, 3,4, of modelsim_files.tcl under pcie_example_design/sim/common, and only line 1..4.
The copy_files now worked without problem, and without modification other lines of the modelsim_files.tcl
However, pcie_example_bfm_zc3dnuy.sv and pcie_example_design_inst_board_bf_ip_aler_conduit_bfm_zc3dnuy.sv where failing in the directory. I copied them from another project.
I had to modify the modelsim under pcie_a10_hip_0_example_design\ip\pcie_example_design\pcie_example_design_DUT\sim\common\modelsim_files.tcl for some files, but not for all, very strange. See attached modelsim_files.txt Any idea?
Could it be that i specified Cyclone10GX, while the design is made for Arria?
regards, Pieter
