Cyclon III starter Kit, flash device

Try creating a flash test program and verify that you are able to read and write to each block of the cfi flash memory. I suppose you could use the memtest template from the Nios IDE. Just create a simple system in SOPC builder, compile it in Quartus II, download the sof file and verify whether you can read/write to each block of cfi flash memory or not.

Hope it will help.

Hi,

Could any one please help me out at what frequency should i have to send the rgb values to the lcd , is it 25 MHZ or 75 MHz .. please let me know i will ver y thankful if you send me the verilog code

I don't know about the CIII kit, but Terasic usually does provide a flash controller in Verilog. It is present in the Control Panel source code.

However Terasic demonstrations are usually too bad for learning purposes, they are barely commented if at all. Furthermore, the control panel doesn't attempt to be very efficient. E.g, most versions of the Terasic control panel doesn't let you erase individual sectors.

It might be much better to use a CFI controller. It shouldn't be too difficult to find one, and I think that you get a clear source code (but of course, not commented) one when instantiating a CFI core in SOPC builder.

I have tried to generate code using SOPC Builder, but the code it has generated for flash is different from other devices.

For devices like SRAM and SDRAM, It has generated controller code, but for Flash it is not generating controller code, instead it has code which works itself as FLASH, code functions as flash (DUMMY FLASH). That code doesnt connect with hardware flash, but inside code it define memory array which saves data and work as flash memory.

This is code generated by SOPC for FLASH

====>>main module is in the bottom

// turn off superfluous verilog processor warnings

// altera message_level Level1

// altera message_off 10034 10035 10036 10037 10230 10240 10030

module cfi_flash_0_lane0_module (

// inputs:

data,

rdaddress,

rdclken,

wraddress,

wrclock,

wren,

// outputs:

q

)

;

output [ 7: 0] q;

input [ 7: 0] data;

input [ 20: 0] rdaddress;

input rdclken;

input [ 20: 0] wraddress;

input wrclock;

input wren;

reg [ 7: 0] mem_array [2097151: 0];

wire [ 7: 0] q;

reg [ 20: 0] read_address;

//synthesis translate_off

//////////////// SIMULATION-ONLY CONTENTS

always @(rdaddress)

begin

if (1)

read_address <= rdaddress;

end

// Data read is asynchronous.

assign q = mem_array[read_address];

initial

$readmemh("cfi_flash_0.dat", mem_array);

always @(posedge wrclock)

begin

// Write data

if (wren)

mem_array[wraddress] <= data; ///memory array

end

//////////////// END SIMULATION-ONLY CONTENTS

//synthesis translate_on

//synthesis read_comments_as_HDL on

// always @(rdaddress)

// begin

// if (1)

// read_address <= rdaddress;

// end

//

//

// lpm_ram_dp lpm_ram_dp_component

// (

// .data (data),

// .q (q),

// .rdaddress (read_address),

// .rdclken (rdclken),

// .wraddress (wraddress),

// .wrclock (wrclock),

// .wren (wren)

// );

//

// defparam lpm_ram_dp_component.lpm_file = "cfi_flash_0.mif",

// lpm_ram_dp_component.lpm_hint = "USE_EAB=ON",

// lpm_ram_dp_component.lpm_indata = "REGISTERED",

// lpm_ram_dp_component.lpm_outdata = "UNREGISTERED",

// lpm_ram_dp_component.lpm_rdaddress_control = "UNREGISTERED",

// lpm_ram_dp_component.lpm_width = 8,

// lpm_ram_dp_component.lpm_widthad = 21,

// lpm_ram_dp_component.lpm_wraddress_control = "REGISTERED",

// lpm_ram_dp_component.suppress_memory_conversion_warnings = "ON";

//

//synthesis read_comments_as_HDL off

endmodule

// turn off superfluous verilog processor warnings

// altera message_level Level1

// altera message_off 10034 10035 10036 10037 10230 10240 10030

//main module

module flash_MAIN (

// inputs:

address,

read_n,

select_n,

write_n,

// outputs:

data

)

;

inout [ 7: 0] data;

input [ 20: 0] address; //address is input which should be output for controller

input read_n;

input select_n;

input write_n;

wire [ 7: 0] data;

wire [ 7: 0] data_0;

wire [ 7: 0] logic_vector_gasket;

wire [ 7: 0] q_0;

//s1, which is an e_ptf_slave

//synthesis translate_off

//////////////// SIMULATION-ONLY CONTENTS

assign logic_vector_gasket = data;

assign data_0 = logic_vector_gasket[7 : 0];

//cfi_flash_0_lane0, which is an e_ram

cfi_flash_0_lane0_module cfi_flash_0_lane0

(

.data (data_0),

.q (q_0),

.rdaddress (address),

.rdclken (1'b1),

.wraddress (address),

.wrclock (write_n),

.wren (~select_n)

);

assign data = (~select_n & ~read_n)? q_0: {8{1'bz}};

//////////////// END SIMULATION-ONLY CONTENTS

//synthesis translate_on

endmodule

Thank You FvM. It worked I am able to read and write using that Flash COntroller.:)

I have another question, DO you have any idea what is maximum speed for writing on to flash? I have tried different speeds 50MHz to 10Khz. I n that 10KHz -125KHz clock works good but if I increase the clock to 250KHz then it skips some address locations. Those locations remains FF only.

Please let me know if you have idea baout Flash Writing speed.

Thank You.