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Altera_Forum
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15 years ago

Current Sink from GPIO 3.3 LVTTL

Hello, I've designed a circuit to generate step and directoin signals for external stepper motor drivers. The input current for these drviers is "-1 mA" which I believe means I need to sink 1mA ...
Altera_Forum's avatar
Altera_Forum
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15 years ago

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Is the FPGA capable of sinking this much current?

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Yes, the output characteristic of FPGA and CPLD I/Os is almost symmetrical. The sink capabilty will be even slightly higher than the source strength. Some numbers can e found in the DC characteristic part of the device data sheet, complete data for individual IO standards and current strength settings can be found in the ibis files.