Current output capability of the CycloneIII I/O cell

I am not an FPGA developer, so please bear with me. I am designing a microprocessor circuit to emulate a 1-wire device connected to a 3.3-V LVTTL output of a Cyclone-III FPGA. 1-wire is a Maxim communication protocol which delivers power to, and allows bidirectional communication with, a sensor over a single pair of wires (signal and ground).

My question is about the output capability of the FPGA I/O Cell that is driving my circuit. The lowest duty cycle of the 1-wire line is ~10% and occurs when sending zeroes from the FPGA to my microcontroller (MCU). Since my MCU draws an average current of 0.7mA, it needs to draw 7 mA during the on-time at the 10% duty cycle to keep it's supply up. Could this damage the FPGA output?

The FPGA powering my device is a EP3C25F256C8N. In the datasheet, I see two relevant specifications regarding output current.

• Absolute maximum ratings (Table 1-1, pg 1-2) list Iout as -25 to 40 mA.
• Single-Ended I/O Standard Specifications (Table 1-13, pg 1-10) shows a "current drive characteristic" of ±4 mA.

The former makes it sound like 7 mA is very unlikely to cause damage. But the latter makes me uncertain that there is not a longer term issue. How should I interpret that latter spec?