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Dominic2's avatar
Dominic2
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10 months ago
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Critical Warning (24567):The design is using an internal oscillator

Build a bitstream for the Agilex-7 evalboard ()

I use the qsys_top system from the GHRD design for that evalboard and add other stuff around the HPS.

I got this message:

Critical Warning (24567): The design is using an internal oscillator along with transceivers, EMIF, MIPI, and PHY Lite interfaces.

I use quartus prime pro 24.3

When i look at the HPS configuration i can see that the external ref clk is enable (HPS_IOB_19)

When I look at the tech view post fitter, the external clk is connected:

Is there something else i should check to fix this critical warning.

When I compile the GHRD design the warning is not present.

I compare all the configuration i can find in both project and everything seem the same.

Thanks

Fpga Devkit
  • Dominic2's avatar
    Dominic2
    10 months ago

    Hi,

    In the same design I added an F-Tile IP and at the fitter step i got this error:

    Intel FPGA IP instantiated in the design require the DEVICE_INITIALIZATION_CLOCK 
option to be set to either OSC_CLK_1_25MHZ, OSC_CLK_1_100MHZ or OSC_CLK_1_125MHZ. This assignment is missing in the QSF file

    The assignment was not present in the QSF:

    set_global_assignment -name DEVICE_INITIALIZATION_CLOCK OSC_CLK_1_125MHZ

    After adding it the fitter completed and the first warning in my original post:

    Critical Warning (24567): The design is using an internal oscillator along with transceivers, EMIF, MIPI, and PHY Lite interfaces.

    Is not present anymore.

    Thanks

3 Replies

  • sstrell's avatar
    sstrell
    Icon for Super Contributor rankSuper Contributor
    10 months ago

    It's a warning, not an error. You don't have to fix it. Check the other stuff you added to the design. Also, does double-clicking the message take you to where the oscillator is being used?

  • Dominic2's avatar
    Dominic2
    Icon for New Contributor rankNew Contributor
    10 months ago

    Hi,

    It is a critical warning and I thinks they should be address and weave if not applicable. But in my case I planned to use the EMIF and I want to be sure that it will not be an issue in the future.

    Double-click on the message does nothing.

    The other stuff in the design is only an avalon bridge (to get regsiter access outside of the Qsys with the HPS) and few dummy register for now. This is pretty limited difference with the reference design.

    Thanks.

  • Dominic2's avatar
    Dominic2
    Icon for New Contributor rankNew Contributor
    10 months ago

    Hi,

    In the same design I added an F-Tile IP and at the fitter step i got this error:

    Intel FPGA IP instantiated in the design require the DEVICE_INITIALIZATION_CLOCK 
option to be set to either OSC_CLK_1_25MHZ, OSC_CLK_1_100MHZ or OSC_CLK_1_125MHZ. This assignment is missing in the QSF file

    The assignment was not present in the QSF:

    set_global_assignment -name DEVICE_INITIALIZATION_CLOCK OSC_CLK_1_125MHZ

    After adding it the fitter completed and the first warning in my original post:

    Critical Warning (24567): The design is using an internal oscillator along with transceivers, EMIF, MIPI, and PHY Lite interfaces.

    Is not present anymore.

    Thanks