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BillM256's avatar
BillM256
Icon for Occasional Contributor rankOccasional Contributor
4 years ago

Create custom logic elements with classic logic symbols for Quartus Block/Schematic Editor

Hello, I’m working on a design using the Quartus Block/Schematic Editor that requires classic TTL-like logic symbols, e.g., and, or, inverter, f/f. It would be useful if I could build my own primit...
Nurina's avatar
Nurina
Icon for Regular Contributor rankRegular Contributor
4 years ago

Hi,


To answer your questions:

  1. Not exactly, I would say it does and you can see them in the block design file created from the Verilog/VHDL code. But when you insert this symbol in a block design file it will appear as a block.
  2. I assume you want them to appear as logic symbols in you block design files. I don't think there's a way to do that. You can double-click on them and it will lead you to open the generated bdf file or the Verilog/VHDLfile.
  3. As far as I know, AHDL will not help. It would be the same as above.
  4. There is no better way to do what you want to do unfortunately. Just give your symbols and their ports a meaningful name so that it'd be easy for you to remember and visualise.


Regards,

Nurina


  • BillM256's avatar
    BillM256
    Icon for Occasional Contributor rankOccasional Contributor
    4 years ago

    Hi Nurina,

    You confirm what I suspected is the case. I'm hoping someone has a solution, so will keep the issue open, but I'm not optimistic.

    Thanks for taking time to help!

    Bill