Forum Discussion
1 Reply
- BoonT_Intel
Frequent Contributor
Hi This is feasible as long as the clock supply to both clk_p and clk_n is meeting the SSTL135 diff IO specification.
Hi
I would like to use CML clock source for EMIF refclk input.
Please see attachment.
OSC and FPGA is connected by AC coupling.
Is this design available for Arria10GX?
Best regards
Hi This is feasible as long as the clock supply to both clk_p and clk_n is meeting the SSTL135 diff IO specification.