Forum Discussion

JRe2s's avatar
JRe2s
Icon for New Contributor rankNew Contributor
1 year ago
Solved

Configuration pins 10M02SCE144I7G

Hello Team, could you review the attached schematics? In particular the config pins of the FPGA? Best regards, Jochen
Board Debug
  • FakhrulA_altera's avatar
    FakhrulA_altera
    1 year ago

    As we haven't received a response to our previous notification, this thread will be transitioned to community support. We hope all your concerns have been addressed. If you have any new questions, please feel free to open a new thread to receive support from Intel experts. Otherwise, community users will continue to assist you here. Thank you.


JRe2s's avatar
JRe2s
Icon for New Contributor rankNew Contributor
1 year ago

Maybe this is wrong wired. Should the JTAGEN be pulled high or low if the pin is not used as an IO?

FvM's avatar
FvM
Icon for Super Contributor rankSuper Contributor
1 year ago
JTAGEN should be pulled high by 10k to enable JTAG pins in user mode. Or configure JTAGEN in dual purpose pin setup as IO to enable JTAG pins unconditionally.
  • JRe2s's avatar
    JRe2s
    Icon for New Contributor rankNew Contributor
    1 year ago

    OK, thanks. The other config pins are wired correct?

    • FvM's avatar
      FvM
      Icon for Super Contributor rankSuper Contributor
      1 year ago
      Yes, think so.