Configuration pins 10M02SCE144I7G

Hello Team,

could you review the attached schematics? In particular the config pins of the FPGA?

Best regards,

Jochen

FakhrulA_altera
1 year ago
As we haven't received a response to our previous notification, this thread will be transitioned to community support. We hope all your concerns have been addressed. If you have any new questions, please feel free to open a new thread to receive support from Intel experts. Otherwise, community users will continue to assist you here. Thank you.

FvM
Super Contributor
1 year ago
Why are you connecting JTAGEN to JTAG connector pin 8?
JRe2s
New Contributor
1 year ago
Maybe this is wrong wired. Should the JTAGEN be pulled high or low if the pin is not used as an IO?
- FvM
  Super Contributor
  1 year ago
  JTAGEN should be pulled high by 10k to enable JTAG pins in user mode. Or configure JTAGEN in dual purpose pin setup as IO to enable JTAG pins unconditionally.
  - JRe2s
    New Contributor
    1 year ago
    OK, thanks. The other config pins are wired correct?
FakhrulA_altera
Regular Contributor
1 year ago
Hi JRe2s,

Alternatively, you can check by referring to the Intel® MAX® 10 Schematic Review Worksheet on Section II, Configuration. (https://www.intel.com/content/www/us/en/content-details/650218/intel-max-10-schematic-review-worksheet.html?DocID=650218)

Regards,
Fakhrul
FakhrulA_altera
Regular Contributor
1 year ago
As we haven't received a response to our previous notification, this thread will be transitioned to community support. We hope all your concerns have been addressed. If you have any new questions, please feel free to open a new thread to receive support from Intel experts. Otherwise, community users will continue to assist you here. Thank you.

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