Communication PC-De0 Nano

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I am trying to use Virtual Jtag starting with a simple verilog design which is a 4 bit counter.

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That's a good start.

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I'm starting by using megawizard manager. I don't quite understand at page 4 of virtual jtag megawizard. What is actually stimulus? I think this is where we define the shifting operation(not sure). How should we know how much delay needed for the stimulus?

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The simulation feature of the component does not work, so don't bother to enter anything in that field. The documents I post will show how the component is broken.

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I also a bit confuse of the diagram block of virtual jtag that shows during megawizard.

Why TDO and ir_out are put at the left side and tck, tdi, ir_in are located at the right side? I think it should be in contrary because TDI(Test data input), TCK(Test clock) and IR_in are the input of the VJI(virtual jtag).

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tdi and ir_in are inputs to your design, but they are outputs of the virtual JTAG component. Similarly ir_out is an output from your design, but its an input to the virtual JTAG component. I know, the names are ambiguous :)

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By the way, how about the progress of your tutorial?

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Not ready for release yet, but I did work on it over the weekend.

Cheers,

Dave