Communication PC-De0 Nano

--- Quote Start ---

I need to make a GUI that could communicate between pc and my De0 nano.

I could make the GUI with QT but I don't know how the communication work.

--- Quote End ---

The USB interface to the DE0-nano is a USB-Blaster.

You can communicate from the host via a couple of mechanisms;

1) SLD Virtual JTAG core, and quartus_stp Tcl procedures

2) JTAG-to-Avalon-MM master and SystemConsole

3) Direct access via FTDI drivers

If you want to communicate via a QT GUI, then you could communicate with (1) and (2) via sockets. Unfortunately SystemConsole has broken fileevent, so servers there can not deal with multiple clients (you have to block on a client socket). Unfortunately Altera do not provide Avalon-MM access functions from quartus_stp, so you'd have to reverse engineer the protocol. (3) also requires reverse engineering the protocols.

I think there is also the option of a JTAG-UART as well, and then communicating via nios2-terminal. However, since this is not a Virtual COM port, I think that solution would be a pain too.

Option (1) is currently the best documented interface for custom communications via USB ... unfortunately, that is being generous (since the documentation has errors ...)

If you are just starting out with FPGAs, then just go an buy an FTDI FT245BM module from Digikey for $20 and use that. The device appears as a Virtual COM port, and the interface logic is pretty easy to implement.

Cheers,

Dave

Thank you so much Dave for your quick reply.

"then just go an buy an FTDI FT245BM module"

(3)Actually De0 nano has already FTDI FT245BL. Should I still buy the FTDI FT245BM module although De0nano has already FTDI chip on board?

Dave, could you also give me a good link or pdf regarding (1) and (3)?

I just don't know where to start.

Thank you again, Dave.

Gunardi

--- Quote Start ---

"then just go an buy an FTDI FT245BM module"

Actually De0 nano has already FTDI FT245BL. Should I still buy the FTDI FT245BM module although De0nano has already FTDI chip on board?

--- Quote End ---

The USB-Blaster circuit is constructed using an FTDI FT245 plus a CPLD. The functionality of this circuit is not documented by Altera (but there are details on the web). I also see that Terasic has stopped publishing the circuit diagram in the schematic too, eg. there is nothing in the DE0-nano schematic.

--- Quote Start ---

could you also give me a good link or pdf regarding (1) and (3)?

--- Quote End ---

The SLD Virtual JTAG interface has a users guide:

http://www.altera.com/literature/ug/ug_virtualjtag.pdf

Everything else has to be reverse engineered using SignalTap II. I've been writing some tutorials on how to use these features. I'll try to finish them and post links.

Cheers,

Dave

Thanks Dave for your quick response.

I will try to read up the pdf immediately.

If it is not too much to ask, when will the tutorials be finished?

Thank you Dave.

--- Quote Start ---

If it is not too much to ask, when will the tutorials be finished?

--- Quote End ---

Whenever I get time :)

Which one sounds the most interesting to you?

Cheers,

Dave

Hello Dave,

I prefer the solution that is onboard solution. I mean why should I buy a new device if there is a solution that already onboard. I think I prefer to use virtual jtag.

As a matter of fact, I found 2 solutions:

1. Buy a usb-ttl 3.3V and connect it to I/O port of De0Nano FPGA board. Of course using this solution I need to write a serial communication protocol.

2. Use another microcontroller board and connect the uc and fpga I/O pin. The protocol between both of them could be serial or paralel protocol(depending on how much pin I would like to use or how much pin is available). At least use 2 wire, if using I2C. The fpga act as master and uc act as slave that transmit or receive data to pc.

I find that both solutions is a waste of resource(my professor think so too especially solution no 2) because I think the De0 nano has to be able to transmit and receive data to pc someway.

Thank you so much Dave.

Wish you could finish it at once. :)

--- Quote Start ---

As a matter of fact, I found 2 solutions:

1. Buy a usb-ttl 3.3V and connect it to I/O port of De0Nano FPGA board. Of course using this solution I need to write a serial communication protocol.

2. Use another microcontroller board and connect the uc and fpga I/O pin. The protocol between both of them could be serial or paralel protocol(depending on how much pin I would like to use or how much pin is available). At least use 2 wire, if using I2C. The fpga act as master and uc act as slave that transmit or receive data to pc.

I find that both solutions is a waste of resource(my professor think so too especially solution no 2) because I think the De0 nano has to be able to transmit and receive data to pc someway.

--- Quote End ---

These are all good solutions. I like that you took the time to think about it.

--- Quote Start ---

Wish you could finish it at once. :)

--- Quote End ---

I'll try to grant your wish. Ping me in a couple of days and see if I have something ready.

Cheers,

Dave

Will do, Dave. :)

Thank you.

Hello Dave,

I have finished the pdf that you gave but not quite get it.

That's why I am trying to use Virtual Jtag starting with a simple verilog design which is a 4 bit counter.

I'm starting by using megawizard manager. I don't quite understand at page 4 of virtual jtag megawizard. What is actually stimulus? I think this is where we define the shifting operation(not sure). How should we know how much delay needed for the stimulus?

I also a bit confuse of the diagram block of virtual jtag that shows during megawizard.

Why TDO and ir_out are put at the left side and tck, tdi, ir_in are located at the right side? I think it should be in contrary because TDI(Test data input), TCK(Test clock) and IR_in are the input of the VJI(virtual jtag).

I think I am asking too much. Hehehe... :) Sorry.

By the way, how about the progress of your tutorial?

Thank you so much

--- Quote Start ---

I am trying to use Virtual Jtag starting with a simple verilog design which is a 4 bit counter.

--- Quote End ---

That's a good start.

--- Quote Start ---

I'm starting by using megawizard manager. I don't quite understand at page 4 of virtual jtag megawizard. What is actually stimulus? I think this is where we define the shifting operation(not sure). How should we know how much delay needed for the stimulus?

--- Quote End ---

The simulation feature of the component does not work, so don't bother to enter anything in that field. The documents I post will show how the component is broken.

--- Quote Start ---

I also a bit confuse of the diagram block of virtual jtag that shows during megawizard.

Why TDO and ir_out are put at the left side and tck, tdi, ir_in are located at the right side? I think it should be in contrary because TDI(Test data input), TCK(Test clock) and IR_in are the input of the VJI(virtual jtag).

--- Quote End ---

tdi and ir_in are inputs to your design, but they are outputs of the virtual JTAG component. Similarly ir_out is an output from your design, but its an input to the virtual JTAG component. I know, the names are ambiguous :)

--- Quote Start ---

By the way, how about the progress of your tutorial?

--- Quote End ---

Not ready for release yet, but I did work on it over the weekend.

Cheers,

Dave