communication between Cyclone III and MAX II in Cyclone III development kit

You are right. I didn't see the Cypress USB 2.0 controller and thought, USB_PHY_xxx are also connected to the FPGA. But they aren't. This mainly emphasizes the question, how the USB operation is intended in the design. Sorry for causing confusion. But the CIII 120 Dev Kit seems to be somewhat mysterious.

I think now, that USB_PHY access is planned through MAX II and the shared bus. But I don't know, if there's is already respective logic included in the factory default MAX II design. Please consider, that I don't have the Dev Kit and possibly missed some documentation or example software updates, that may clarify the said questions.