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Shubhall's avatar
Shubhall
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3 years ago

Clocking Network (Quartus prime pro 20.2)

Hi, I generated low latency MAC example design from the Quartus prime pro 20.2(screenshot attached for reference - 10G_base_R_design_example.png) ; in the ATX pll IP for PHY, I did not choose any ...
Kshitij_Intel's avatar
Kshitij_Intel
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3 years ago

Hi Shubhall,


For the best jitter performance, Intel recommends using a reference clock within the same bank as the transceiver PLL (ATX PLL, fPLL) that the reference clock is driving.


If possible, please put the ATX PLL or fPLL in the same bank as reference clock in Assignment Editor.


Thank you

Kshitij Goel


  • Shubhall's avatar
    Shubhall
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    3 years ago

    okay ...