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Shubhall's avatar
Shubhall
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3 years ago

Clocking Network (Quartus prime pro 20.2)

Hi, I generated low latency MAC example design from the Quartus prime pro 20.2(screenshot attached for reference - 10G_base_R_design_example.png) ; in the ATX pll IP for PHY, I did not choose any ...
Shubhall's avatar
Shubhall
Icon for New Contributor rankNew Contributor
3 years ago

I am getting this warning while generating .sof

ATX/FPLL < dut_inst|wrapper_inst|atx_pll_inst|altera_xcvr_atx_pll_ip_inst|a10_xcvr_atx_pll_inst|twentynm_atx_pll_inst > is not placed in the same bank as the reference clock.

Can I ignore this warning or do I have to compulsory use the bonded/xN clocking?