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ymiler's avatar
ymiler
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2 years ago

clock gated conversion

Hello, I'm running Quartus 22.3 building for an S10 FPGA. Since my FPGA is prototype, the project includes several clock gated to solve it I added the following command to the QSF : set_glob...
Fpga Devkit
Adrien_Lacroix's avatar
Adrien_Lacroix
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1 year ago

Hello,
I am facing the same issue trying to synthetize my design into a Stratix 10 (1SG280H).
I am using this FPGA for ASIC prototyping and I also have several (and cascaded) gated clocks.
Do you have a solution to correctly convert those gated clock into clock enable ?
I have tried so far:

  1. using "set_global_assignment -name SYNTH_GATED_CLOCK_CONVERSION ON". It does not work as several clocks are not correctly converted.
  2. using a module "stratix10_clk_ctrl" but it does not work as it seems that this module does not accept to receive a gated clock in input (so it does not work for cascaded gated clock)

I am using Quartus Prime Pro 24.2.0

Thank you,

Adrien

  • ymiler's avatar
    ymiler
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    1 year ago

    Hi Adrien

    I still haven't received a solution to my issue.

    However, I have opened a case on the Altera support website.

    As far as I know, they are working on finding a solution in their next release.