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ymiler's avatar
ymiler
Icon for Contributor rankContributor
1 year ago

clock gated conversion

Hello, I'm running Quartus 22.3 building for an S10 FPGA. Since my FPGA is prototype, the project includes several clock gated to solve it I added the following command to the QSF : set_glob...
Fpga Devkit
ymiler's avatar
ymiler
Icon for Contributor rankContributor
1 year ago

Hi

Following to you answer you use:

gcw__ckltchand gcw__ckltchand_1 (
.CP(i_clk),
.E(i_en),
.TE(),
.Q(gclk)
);

Is it Altera primitive code ?

RichardT_altera's avatar
RichardT_altera
Icon for Super Contributor rankSuper Contributor
1 year ago

No, "gcw__ckltchand" is the module instantiation that you provided in your previous post. Posted on 18th April.

// Gated Clock Latch
module gcw__ckltchand (
TE,
E,
CP,
Q
);
input TE;
input E;
input CP;
output Q;

wire EN_TE;
reg CPEN;

or or1 (EN_TE,E,TE);


always @(EN_TE or CP)
if(~CP) CPEN <= EN_TE;

and an1 (Q,CPEN,CP);

endmodule //gcw__ckltchand