Forum Discussion
ymiler
Contributor
Contributorclock gated conversion
Hello, I'm running Quartus 22.3 building for an S10 FPGA. Since my FPGA is prototype, the project includes several clock gated to solve it I added the following command to the QSF : set_glob...
ymilerContributor
ContributorHi
Following to you answer you use:
gcw__ckltchand gcw__ckltchand_1 (
.CP(i_clk),
.E(i_en),
.TE(),
.Q(gclk)
);
Is it Altera primitive code ?
RichardT_altera
Super Contributor
Super ContributorNo, "gcw__ckltchand" is the module instantiation that you provided in your previous post. Posted on 18th April.
// Gated Clock Latch
module gcw__ckltchand (
TE,
E,
CP,
Q
);
input TE;
input E;
input CP;
output Q;
wire EN_TE;
reg CPEN;
or or1 (EN_TE,E,TE);
always @(EN_TE or CP)
if(~CP) CPEN <= EN_TE;
and an1 (Q,CPEN,CP);
endmodule //gcw__ckltchand
- ymiler
Hi
I found the issue,
My design includes two clock gates in a row. When I remove the second clock gate, Quartus successfully convert the first clock gate.
Why does this happen? Is there any option to resolve it?
Bu the way, the message from Quartus is unclear in understanding the issue:
Reason not converted :
Found unsupported gate top|cnvr|cnvr_tlgc_inst|cnvr_scu_ins|cnvr_scu_seq_ins|block_gated_clk_seq_ins|stdc__clk_enable_nlt_reg|gcw__ckltchand|CPEN in the gated clock tree
