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ymiler's avatar
ymiler
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2 years ago

clock gated conversion

Hello, I'm running Quartus 22.3 building for an S10 FPGA. Since my FPGA is prototype, the project includes several clock gated to solve it I added the following command to the QSF : set_glob...
Fpga Devkit
RichardT_altera's avatar
RichardT_altera
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2 years ago

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ymiler's avatar
ymiler
Icon for Contributor rankContributor
2 years ago

I replaced my clock gate instance to:

gcw__ckltchand gcw__ckltchand_1 (
.CP(i_clk),
.E(i_en),
.TE(),
.Q(gclk)
);

then I re-run synthesis and get the message:

Gated clock:

top|cnvr|cnvr_tlgc_inst|cnvr_scu_ins|cnvr_scu_dig_cgu_ins|scu_top_cg_aux_clk_ins|cell__clk_enable_nlt_reg|gcw__ckltchand|an1

Base clock :

top|cnvr_pll1_inst|iopll_0|stratix10_altera_iopll_i|outclk[0]

Converted to Clock enable :

No

Reason not converted :

Found unsupported gate top|cnvr|cnvr_tlgc_inst|cnvr_scu_ins|cnvr_scu_seq_ins|block_gated_clk_seq_ins|stdc__clk_enable_nlt_reg|gcw__ckltchand|CPEN in the gated clock tree

Could you explain why Quartus did not succeed to converted?