Contributor
Super ContributorIt would help to see some code and understand why you have so many gated clocks to begin with. It would be much better to use clock enables instead of gated clocks.
ContributorHi
Original code is ASIC RTL who use clock gate to decrease power supply.
Here the clock gated code:
// Gated Clock Latch
module gcw__ckltchand (
TE,
E,
CP,
Q
);
input TE;
input E;
input CP;
output Q;
wire EN_TE;
reg CPEN;
or or1 (EN_TE,E,TE);
always @(EN_TE or CP)
if(~CP) CPEN <= EN_TE;
and an1 (Q,CPEN,CP);
endmodule //gcw__ckltchand
Super ContributorBy adding the top.v file with attached code. The tool able to recognize the gated clock and converted to use clock enables.
Info(19019): Convert gated clock gcw__ckltchand_1|Q
module top (
input i_rst_n,
input i_en,
input i_clk,
input i_data,
output reg o_data
);
wire gclk;
gcw__ckltchand gcw__ckltchand_1 (
.CP(i_clk),
.E(i_en),
.TE(),
.Q(gclk)
);
always @(posedge gclk or negedge i_rst_n) begin
if (!i_rst_n) begin
o_data <= 1'b0;
end else begin
o_data <= i_data;
end
end
endmodule
Perhaps you could check your design hierarchy to see what might be going wrong.
You could also share a simple testcase .qar file (Project > Archive Project) that you expect the tool to convert the gated clock but it does not.
Regards,
Richard Tan
ContributorHI
I tried to create a simple test case which includes :
PLL - > clock gate -> counter
I have the flag :
set_global_assignment -name SYNTH_GATED_CLOCK_CONVERSION ON
But the Quartus didn't convert the clock gate ,
Do you know why ?
I attached QAR archive file of my minimal test
