Forum Discussion

New Contributor

6 years ago

Channel to Channel skew with ALTDDIO_OUT

Hello, I am using couple of ALTDDIO_OUT channels in Cyclone 10 LP and map them onto true LVDS pins. Is there a way to get the channel to channel skew analysis by the Timing Analyzer ? when I try the...

Rahul_S_Intel1

Frequent Contributor

6 years ago

To answer your question , the TCCS value will be provided only for the serdes , you can find the calculation from the IO user guide of c10lp

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/cyclone-10/c10lp-51003.pdf

Forum Discussion

Channel to Channel skew with ALTDDIO_OUT

Recent Discussions

Agilex™ 7 FPGA M-Series Development Kit_HBM2e Edition_REVB2_Altera

Agilex 7 R-Tile PIPE Direct endpoint receives Set_Slot_Power_Limit, but no Config TLPs

SyncE clock as the reference for DDR, HBM, and FPGA control interfaces in the Agilex M-Series design

R-tile CXL base hard IP example for the Agilex 7 M-series Dev Kit (DK_DEV_AGM039EA) does not work

PCIe Root Complex on DK-A5E013BM16AEA